1. Field of the Invention
The present invention relates to a method of forming a trench isolation in a semiconductor device, and more specifically, to a method of forming trench isolation in a semiconductor device.
2. Description of the Related Art
Shallow trench isolation (STI) technology is considered a more viable isolation technology than traditional local oxidation of silicon (LOCOS) because STI does not create what is known as “bird's beaks” of LOCOS. As such, STI achieves reduced conversion differences and occupies less area.
The conventional STI fabrication techniques include forming a pod oxide on a semiconductor substrate surface, forming a pad nitride on the pad oxide, forming a pattern layer for opening an isolation region in the substrate surface, anisotropically etching the opened region from the pad oxide and pad nitride to form a trench in the semiconductor substrate, forming a thermal oxide liner in the trench and then filling the trench with insulating material, such as silicon oxide.
During subsequent processing, the pad oxide and pad nitride layers are removed followed by formation of active regions, which typically involve masking, ion implantation, and cleaning steps. The cleaning steps may include cleaning before deposition of sacrificial oxide layer, and cleaning before ion implantation for well formation and the threshold voltage. Since the corners of the STI define the boundaries between active and field regions, they are affected by such cleaning steps as well as a wet etching step for forming the sacrificial oxide layer. The wet etching step typically uses sulfuric acid and hydrofluoric acid solutions. These acidic solutions may isotropically remove the top corners of STI leaving a void or “divot” 16 in the oxide fill as shown in FIG. 8.
The STI divots are problematic in various respects. For instance, STI divots are responsible for high field edge leakage, particularly with shallow source/drain junctions. Further, the growth of gate oxide in the divot area is abnormal, resulting in thinner gate oxide layer and thicker gate polysilicon at its edges. Therefore, the threshold voltage is altered and hot carrier injection (HCI) due to electric field concentration may occur.